One of the common elements required in electrical circuit devices is the simple pullup (or pulldown device) from an active device to one of the power supply buses. The pullup is simple if used to construct a circuit using discrete components, in that, all that is required is selecting a resistor of the desired resistance and tolerance, connecting it between an active device, such as an n-channel MOS transistor, and V.sub.cc and the transistor's output would be pulled up to V.sub.cc once the transistor is turned off. With the advent of the integrated circuit (IC) however, fabricating a resistance onto a wafer substrate, such as silicon or gallium arsenide, takes special consideration particularly when resistivity and tolerances play an important part in circuit operation.
For example, as SRAMs have evolved from the small 4 Kb memory arrays to more densely packed array sizes, tolerances of pullup resistances (or pullup loads) had to be tightly controlled. In order to minimize standby current many fabrication processes adopted using an active device as the pullup. In CMOS fabrication it is common to see a PMOS transistor acting as an active load device by providing a current path between a memory cell pulldown transistor and the power supply bus. In this manner the PMOS transistor could be gated on only when the desired line was to be pulled to V.sub.cc and turned off otherwise, thereby virtually eliminating leakage current and minimizing standby current for the SRAM device as a whole.
A problem with TFTs is high off-current due to high electric fields between the channel and drain region of the TFT. To reduce this off current, one can offset the drain from the edge of the gate such that a region of low doped or undoped, non-gated TFT poly lies between the gated channel and the TFT drain. Since many TFTs are bottom gated, a photo step defines the location of the drain, and is therefore susceptible to misalignment. The size of the offset region has a large impact on the TFT device performance.
Ongoing efforts to improve active loads has brought about the development of thin film transistors (TFTs) in attempts to provide low leakage current as well as high noise immunity. The following two articles, hereby incorporated by reference, discuss TFT development in SRAMs. The first article is "A POLYSILICON TRANSISTOR TECHNOLOGY FOR LARGE CAPACITY SRAMs," by Ikeda et al., IEDM 1990, pp. 469-472. The second article is "A 25 .mu.m.sup.2, New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity, " by Yamanaka et al , IEDM 1988, pp. 48-51.
The present invention, however, introduces a TFT that has lightly doped drain regions (LDDs) and/or high resistive regions (loads) that are self-aligned to a recessed TFT gate. This invention provides self-aligned offset regions or high resistance regions to lower the off current of the TFTs without additional photo steps. In fact fewer masking steps are required.